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1 ISL35411 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2010. all rights reserved all other trademarks mentioned are the property of their respective owners. quad driver ISL35411 the ISL35411 is a quad de-emphasis driver with extended functionality for advanced protocols operating with line rates up to 11.1 gbps such as infiniband (qdr) and 40g ethernet (40gbase-cr4/sr4). the ISL35411 is a high-speed driver/limiting amplifier with built in de-emphasis to drive twin-axial copper cables and compensate for the frequency dependent attenuation of pcb traces such as the sfi channel in the 10g sfp+ specification (sff-8431). used in conjunction with intersil?s isl36411 receive-side equalizer, ISL35411 enables active copper cable assemblies that support 10g serial data transmission over >15m of twin-axial copper cables. operating on a single 1.2v power supply, the ISL35411 enables per channel throughp uts of 10gbps to 11.1gbps. the ISL35411 uses current mode logic (cml) input/output and is packag ed in a 4mmx7mm 46 lead qfn. features ? supports four channels with data rates up to 11.1gbps ? low power (90mw per channel) ?low latency ? adjustable output de-emphasis ? four drivers in a 4mmx7mm qfn package for straight route-through architecture & simplified routing ? supports 64b/66b encoded data ? long run lengths ? line silence preservation ? 1.2v supply voltage ?tx_disable applications ? qsfp active copper cable modules ? infiniband (qdr) ? 40g ethernet (40gbase-cr4/sr4) ? 100g ethernet (100gbase-cr10/sr10) ? high-speed active cable assemblies ? high-speed printed circuit board (pcb) traces benefits ? thinner gauge cable ? extends cable reach greater than 3x ?improved ber typical application circuit v dd cp losb in1[p,n] in2[p,n] in3[p,n] in4[p,n] out1[p,n] out2[p,n] out3[p,n] out4[p,n] dt 1.2v 10nf 100pf rx1[p,n] rx2[p,n] rx3[p,n] rx4[p,n] host asic active copper cable assembly 8-pair differential 100o twin-axial cable = 10m 28awg connector paddle card isl36411 1.2v 100pf v dd de tdsbl in1[p,n] in2[p,n] in3[p,n] in4[p,n] out1[p,n] out2[p,n] out3[p,n] out4[p,n] 1.2v 10nf 100pf ISL35411 tx4[p,n] tx3[p,n] tx2[p,n] tx1[p,n] host asic connector paddle card 0.1f 0.1f 0.1f 0.1f fabric switch host channel adapter 10nf 100pf 10nf 1.2v 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f dt march 25, 2010 fn6971.1
ISL35411 2 fn6971.1 march 25, 2010 pin configuration ISL35411 (46 ld qfn) top view ordering information part number (notes 1, 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL35411drz-ts ISL35411drz 0 to +85 46 ld qfn (7?? 100 pcs.) l46.4x7 ISL35411drz-t7 ISL35411drz 0 to +85 46 ld qfn (7? 1k pcs.) l46.4x7 notes: 1. ?-ts? and ?-t7? suffix is for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin pl ate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). inte rsil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device in formation page for ISL35411 . for more information on msl please see techbrief tb363 . v dd in1[p] in1[n] tdsbl1 v dd in2[p] in2[n] gnd nc dt1 de1a de1b gnd nc 1 2 3 4 5 6 7 46 45 44 43 42 41 40 8 9 10 11 12 13 14 15 39 16 17 18 19 20 21 22 23 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 tdsbl2 v dd in3[p] in3[n] tdsbl3 v dd in4[p] in4[n] out1[p] out1[n] v dd v dd out2[p] out2[n] v dd v dd out3[p] out3[n] v dd v dd out4[p] out4[n] v dd v dd exposed pad de2b nc gnd dt2 tdsbl4 de2a nc gnd (gnd)
ISL35411 3 fn6971.1 march 25, 2010 pin descriptions pin name pin number description v dd 1, 5, 9, 13, 24, 27, 28, 31, 32, 35, 36, 39 power supply. 1.2v supply voltage. the use of parallel 100pf and 10nf decoupling capacitors to ground is recommended for each of these pi ns for broad high-frequ ency noise suppression. in1[p,n] 2, 3 driver 1 differential input, cml. the us e of 100nf low esl/esr mlcc capacitor with at least 6ghz frequency respon se is recommended. tdsbl1 4 transmit disable pin for driver 1. disables the driver when pulled to vdd. connected to ground for normal operation. in2[p,n] 6, 7 driver 2 differential input, cml. the us e of 100nf low esl/esr mlcc capacitor with at least 6ghz frequency respon se is recommended. tdsbl2 8 transmit disable pin for driver 2. disables the driver when pulled to vdd. connected to ground for normal operation. in3[p,n] 10, 11 driver 3 differential input, cml. the use of 100nf low esl/esr mlcc capacitor with at least 6ghz frequency respon se is recommended. tdsbl3 12 transmit disable pin for driver 3. disables the driver when pulled to vdd. connected to ground for normal operation. in4[p,n] 14, 15 driver 4 differential input, cml. the use of 100nf low esl/esr mlcc capacitor with at least 6ghz frequency respon se is recommended. tdsbl4 16 transmit disable pin for driver 4. disables the driver when pulled to vdd. connected to ground for normal operation. gnd 17, 23, 40, 46 these pins should be grounded. dt2 18 detection threshold for drivers 3 and 4. reference dc voltage thre shold for input signal power detection. data output s out3 and out4 are muted when the power of in3 and in4, respectively, fall below the threshold. tie to gr ound to disable electrical idle preservation and always enable the limiting amplifier. de2[a,b,] 19, 20 control pins for setting de-emphasis on drivers 3 and 4. cmos logic inputs. pins are read as a 2-digit number to set the de-emphasis level. a is the msb, and b is the lsb. pins are internally pulled up an d pulled down with 25k resistors. nc 21, 22, 41, 45 not connected: do not make any connections to these pins. out4[n,p] 25, 26 driver 4 differential output, cml. the use of 100nf low esl/esr mlcc capacitor with at least 6ghz frequency respon se is recommended. out3[n,p] 29, 30 driver 3 differential output, cml. the use of 100nf low esl/esr mlcc capacitor with at least 6ghz frequency respon se is recommended. out2[n,p] 33, 34 driver 2 differential output, cml. the use of 100nf low esl/esr mlcc capacitor with at least 6ghz frequency respon se is recommended. out1[n,p] 37, 38 driver 1 differential output, cml. the use of 100nf low esl/esr mlcc capacitor with at least 6ghz frequency respon se is recommended. de1[b,a] 42, 43 control pins for setting de-emphasis on dr ivers 1 and 2. cmos logic inputs. pins are read as a 2-digit number to set the de-emphasis level. a is the msb, and b is the lsb. pins are internally pulled up an d pulled down with 25k resistors. dt1 44 detection threshold for drivers 1 and 2. reference dc voltage thre shold for input signal power detection. data output s out1 and out2 are muted when the power of in1 and in2, respectively, fall below the threshold. tie to gr ound to disable electrical idle preservation and always enable the limiting amplifier. exposed pad - exposed ground pad. for proper electr ical and thermal performan ce, this pad should be connected to the pcb ground plane.
ISL35411 4 fn6971.1 march 25, 2010 absolute maximum ratings thermal information supply voltage (v dd to gnd) . . . . . . . . . . . . -0.3v to 1.5v voltage at all input pins . . . . . . . . . . . . . . . . -0.3v to 1.5v esd ratings human body model high-speed pins . . . . . . . . . . . . . . . . . . . . . . . . . 1.5kv all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kv thermal resistance (typical) ja (c/w) jc (c/w) 46 ld qfn package (notes 4, 5) . . 33 2.8 operating ambient temperature range . . . . . . 0c to +85c storage ambient temperature range . . . . -55c to +150c maximum junction temperature . . . . . . . . . . . . . . . +125c pb-free reflow profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. note: 4. ja measured in free air with the component mounted on a high effective thermal conductivity test board with ?direct attach? features. see tech brief tb379. 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. operating conditions parameter symbol condition min typ max units supply voltage v dd 1.1 1.2 1.3 v operating ambient temperature t a 02585c bit rate nrz data applied to any channel 10 11.1 gbps control pin characteristics v dd = 1.2v, t a = +25c, and v in = 600mv p-p , unless otherwise noted. parameter symbol condition min typ max units input low logic level v il 0350mv input high logic level v ih 750 v dd mv input current current draw on digi tal pin, i.e., de[k][a,b] 100 200 a electrical characteristics v dd = 1.2v, t a = +25c, and v in = 600mv p-p , unless otherwise noted. parameter symbol condition min typ max units notes supply current i dd de-emphasis disabled 260 ma 6 de-emphasis enabled 300 ma 6 transmit disable mode 5.6 ma 6 input amplitude range v in measured differentially at data source 120 1600 mv p-p dc differential input resistance measured on input channel in[k] 80 100 120 dc single-ended input resistance measured on input channel in[k]p or in[k]n, with respect to v dd 40 50 60 input return loss limit (differential) s dd 11 100mhz to 4.1ghz see 7 db 7 4.1ghz to 11.1ghz see 8 db 8 input return loss limit (common mode) s cc 11 100mhz to 2.5ghz see 9 db 9 2.5ghz to 11.1ghz -3 db 12 input return loss limit (com. to diff. conversion) s dc 11 100mhz to 11.1ghz -10 db 12 output amplitude range v out measured differentially at out[k]p and out[k]n with 50 load on both output pinsde-empha sis disabled 450 700 820 mv p-p differential output impedance measured on out[k] 80 105 120
ISL35411 5 fn6971.1 march 25, 2010 output return loss limit (differential) s dd 22 100 mhz to 4.1ghz see 7 db 7 4.1ghz to 11.1ghz see 8 db 8 output return loss limit (common mode) s cc 22 100mhz to 2.5ghz see 9 db 9 2.5ghz to 11.1ghz -3 db 12 output return loss limit (com. to diff. conversion) s dc 22 100mhz to 11.1ghz -10 db 12 residual deterministic jitter 11.1gbps; no channel attenuation; de-emphasis disabled 0.1 ui 10 random jitter 0.7 ps rms output transition time t r , t f 20% to 80% 35 ps 11 minimum de-emphasis level 0db maximum de-emphasis level 4db de-emphasis resolution 0.5 db notes: 6. temperature = +25c, v dd = 1.2v. 7. maximum reflection coefficient give n by equation sddxx(db)= -12 + 2* (f ), with f in ghz. esta blished by characterization and not production tested. 8. maximum reflection coefficient given by equation sddxx(db )= -6.3 + 13log10(f/5.5), with f in ghz. established by characterization and no t production tested. 9. reflection coefficient given by equation sccxx(db) < -7 + 1.6*f, with f in ghz. established by characterization and not production tested. 10. measured using a prbs 2 7 -1 pattern. 11. rise and fall times measured with a 1-1-1-1-1-1-1-1-0-0-0-0- 0-0-0-0 test pattern at 11.1gbps with no channel loss and disabled de -emphasis. 12. limits established by characterizat ion and are not production tested. electrical characteristics v dd = 1.2v, t a = +25c, and v in = 600mv p-p , unless otherwise noted. (continued) parameter symbol condition min typ max units notes
ISL35411 6 fn6971.1 march 25, 2010 operation the ISL35411 is an advanced driver for high-speed interconnects. a functional diagram of ISL35411 is shown in figure 4. in addition to a de-emphasis circuit to compensate for channel loss and improve signal fidelity, the ISL35411 contains unique integrated features to preserve special signaling protocols typically broken by other drivers. the signal detect function is used to mute the channel output when the equalized signal falls below the level determined by the detection threshold (dt) pin voltage. this function is intended to preserve periods of line silence as illustrated in figure 4, the core of the high-speed signal path in the ISL35411 is a sophisticated driver followed by a de-emphasis circuit. the device applies pre-distortion to compensate for skin effect loss, dielectric loss, and impedance discontinuities in the transmission channel. typical performance characteristics performance is measured using the test setup illustrated in fi gure 1. the signal from the pattern generator is launched into the chip evaluation board. the ISL35411 output signal is then visualized on a scope to determine signal integrity parameters such as jitter. figure 1. device characterization test setup 2a. de-emphasis 0 2b. de-emphasis 6 figure 2. ISL35411 10.3125gbps output; no channel; prbs-31 figure 3. ISL35411 10.3125 gbps output after a 22-inch fr-408 trace, prbs-31; de-emphasis 6 p attern generator ISL35411 eval board o scillo sco p e
ISL35411 7 fn6971.1 march 25, 2010 adjustable de-emphasis ISL35411 features a settable de-emphasis driver for custom signal restoration. the voltages at the de pins are used to determine the de-emphasis levels of each 2-channel group ? from 0db to 4db in 0.5db increments. for each two of the four channels the [a] and [b] control pins de[k] are associated with a non binary word. [a] and [b] can take one of three different values: ?low?, ?middle?, or ?high?. this is achieved by leaving the de pins floating or connecting them either to vdd or gnd through 0 resistors. table 1 defines the mapping from the 2-bit de word to the 7 possible de-emphasis levels. line silence/quiescent mode the ISL35411 is capable of maintaining periods of line silence by monitoring its input pins for loss of signal (los) conditions and subsequently muting the output drivers when such a condition is detected. a reference voltage applied to the detection threshold dt[k] pins is used to set the los threshold of the internal signal detection circuitry. for most applications, it is recommended to leave the dt pin floating at its default internal bias. if the sensitivity of the detection threshold needs to be adjusted, the dt voltage can be adjusted with an external pull-up resistor. the resistor values should be validated on an application-specific basis. connect the dt pin to ground in order to disable this feature and prevent the outputs from muting during line silence. pcb layout considerations because of the high speed of the ISL35411 signals, careful pcb layout is critical to maximize performance. the following guidelines should be adhered to as closely as possible: ? all high speed differential pair traces should have a characteristic impedance of 50 with respect to ground plane and 100 with respect to each other. ? avoid using vias for high speed traces as this will create discontinuity in the traces? characteristic impedance. ? input and output traces need to have dc blocking capacitors (100nf). capacitors should be placed as close to the chip as possible. ? for each differential pair, the positive trace and the negative trace need to be of the same length in order to avoid intra-pair skew. a serpentine technique may be used to match trace lengths. ? maintain a constant solid ground plane underneath the high-speed differential traces. ? each vdd pin should be connected to 1.2v and also bypassed to ground through a 10nf and a 100pf capacitor in parallel. minimize the trace length and avoid vias between the vdd pin and the bypass capacitors in order to maximize the power supply noise rejection. ? if 4 channels of the device are set to the same boost, then the quantity of cp resistors can be reduced by tying both cp pins together. signal detector in[p] in[n] dt out[n] out[p] adjustable de-emphasis dea deb limiting amplifier output driver pre- driver tdsbl figure 4. functional diagram of a single channel within the ISL35411 table 1. mapping between de-emphasis level and de-pin connectivity de pin connection nominal de-emphasis level; 10.3125gbps to 11.1gbps (db) de-emphasis setting de[a] de[b] open open 0 0 open gnd 0.6 1 open vdd 1.1 2 gnd open 1.6 3 gnd gnd 2.3 4 gnd vdd 3 5 vdd open 4 6
ISL35411 8 fn6971.1 march 25, 2010 application information typical application schematic for ISL35411 is shown in figure 5. 1 2 3 4 5 6 7 8 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 16 17 18 19 20 21 22 23 9 10 11 12 13 14 15 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 de2[a ] de2[b] de1[a] de 1[b] 1.2v 1.2v 1.2v in1[p] in1[n] in2[p] in2[n] in3[p] in3[n] in4[p] in4[n] out2[p] out2[n] out4[p] out4[n] out1[p] out1[n] out3[p] out3[n] a ISL35411 1.2v 100pf* 10nf bypass circuit for each v dd pin (*100pf capacitor should be positioned closest to the pin) de-emphasis control for channels 1 and 2 tdsbl4 gnd dt1 de-emphasis control for channels 3 and 4 a) dc blocking capacitors = x7r or cog 0.1f (>6ghz bandwidth) 1.2v dt2 nc 1.2v tdsbl1 1.2v 1.2v tdsbl2 1.2v tdsbl3 nc gnd 1.2v gnd nc nc gnd 1.2v 1.2v 1.2v figure 5. typical application reference schematic for ISL35411 notes: 13. see ?adjustable de-emphasis? on page 7 for information on how to connect the de pins. 14. see ?line silence/quiescent mode? on page 7 for details on dt pin operation.
ISL35411 9 fn6971.1 march 25, 2010 about q:active ? intersil has long realized that to enable the complex server clusters of next generation datacenters, it is critical to manage the signal integrity issues of electrical interconnects. to address this, intersil has developed its groundbreaking q:active? product line. by integrating its analog ics inside cabling interconnects, intersil is able to achieve unsurpassed improvements in reach, power consumption, latency, and cable gauge size as well as increased airflow in tomorrow's datacenters. this new technology transforms passive cabling into intelligent "roadways" that yield lower operating expenses and capital expenditures for the expanding datacenter. intersil lane extenders allow greater reach over existing cabling while reducing the need for thicker cables. this significantly reduces cable weight and clutter, increases airflow, and improves power consumption.
ISL35411 10 intersil products are manufactured, assembled and tested utilizing iso9000 qu ality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, th e reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accura te and reliable. however, no re sponsibility is assumed by inte rsil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which ma y result from its use. no licen se is granted by implication o r otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn6971.1 march 25, 2010 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manuf acture of high-performance analog semiconductors. the company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. intersil's product families address power management and analog signal processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentat ion and related parts, please see the respective device information page on intersil.com: ISL35411 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php revision history the revision history provided is for informat ional purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 3/16/10 fn6971.1 page 4: ? control pin characteristics: change ?output low/high? to ?input?, change symbols to vil/vih; condition ? blank vil : min 0, max 350, delete typical ?0? vih; min 750 mv ? input current: typ 100; max 200 ? added high-speed pins to esd ratings as follows to abs max ratings: esd ratings human body model high-speed pins 1.5kv all other pins 2kv ? removed the fland pattern on page 9 due to information already in outline drawing. 2/8/10 fn6971.0 initial release
ISL35411 11 fn6971.1 march 25, 2010 package outline drawing l46.4x7 46 lead thin quad flat no-lead plastic package (tqfn) rev 0, 9/09 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view c 0.152 ref 0 . 05 max. 0 . 00 min. 5 4.00 a b 7.00 (4x) 0.05 6 pin 1 index area 39 46 2.80 42x 0.40 exp. dap 15 1 38 23 46x 0.40 16 6 5.60 ( 6.80 ) ( 5.50 ) ( 46 x 0.60) (46x 0.20) ( 42x 0.40) ( 3.80 ) ( 2.50) 2.50 0.1 0.10 46x 0.20 a mc b 4 5.50 0.1 exp. dap 0.70 0.05 see detail "x" seating plane 0.05 0.10 c c c 24 side view pin 1 index area

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